The CHIPS research group is dedicated to pioneering advancements in chip and package-scale communication infrastructures, which are essential for the next generation of computer architectures. We focus on three primary areas: general-purpose many-core systems, supercomputers, and deep neural network (DNN) accelerators. Each area presents unique challenges and opportunities for innovation in how data is exchanged and processed. For general-purpose many-core systems, we are developing scalable, high-throughput communication frameworks that enhance parallelism and efficiency. In the realm of supercomputers, our work aims to minimise latency and maximise bandwidth to handle increasingly complex simulations and computations. Our efforts in DNN accelerators focus on optimising dataflow between highly specialised processing units to significantly speed up artificial intelligence (AI) and machine learning (ML) tasks. At the heart of all these explorations lies a key enabling technology: wireless interconnects within chips and packages. Using this technology, we seek to reduce wiring complexity, enhance data transfer rates, and improve overall system flexibility. Through collaborative research and technological exploration, our group aims to set the foundation for the computational capabilities of tomorrow, ensuring that advancements in hardware keep pace with the ever-growing demands of software applications and computational theory.